An integrated circuit (IC) device may be formed with millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate (wafer). For the IC device to be functional, multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring (interconnect) structures, are fabricated using BEOL (back end of line) techniques to connect the circuit elements distributed on the surface of the device.
In general, damascene techniques involve depositing an interlevel dielectric (ILD) layer, such as silicon dioxide, forming an opening in the ILD, overfilling the opening with a metal such as copper (Cu), and removing excess metal using chemical mechanical polishing (CMP), resulting in a planarized interconnect structure. This results in a single wiring level or interconnect level of an overall interconnect structure having many wiring levels. The opening in the interconnect level may be a trench running essentially parallel to the surface of the integrated circuit (IC) chip, and a filled trench is referred to as a “wire” or a “line”. A wire is used to route signals from a first location on the wafer to a second location remote from the first location. The trench for forming the wire may extend only partially (e.g., halfway) into the thickness of the ILD, from the top surface thereof.
Alternatively, an opening in the interconnect level may be a via, extending perpendicular to the surface of IC completely through the ILD for connecting an overlying wire of a higher wiring level or of the present wiring level to an underlying wire of a lower wiring level. A filled via is typically simply referred to as a via or as a plug particularly when connecting to an underlying first metallization (M1) or to an element of an underlying MOS (metal oxide semiconductor) structure.
In dual damascene techniques, the opening in the ILD comprises a lower contact or via hole portion in communication with an upper trench portion, and both the via and the trench portions are simultaneously filled. There are three main sequences (via-first, trench-first, buried-via) for forming dual-damascene differing in the sequence in which the via and trench are patterned and etched, but the resulting structure is generally the same for all three.
As technology nodes reach 45 nm and beyond, BEOL technologies must be continuously optimized through changes in process flows and material used in order to build high performance structures. For exampler as critical dimensions decrease, etching of small profiles using thin masking layers becomes increasingly problematic with regard to etch profile control (controlling shape of hole or trench being formed), control of etching damage and residues, and control of critical dimensions such as line edge roughness (LER) and line width roughness (LWR). Moreover, the control of uniformity and variability also becomes increasingly problematic where microloading, caused by different etch rates for densely packed features verses open or isolated features, results in non-uniformity.
As the semiconductor fabrication industry moves towards the 32 nm device generation, thinner photoresist layers are needed to, e.g., enable and extend lithographic printing, which is driving increased use of thinner hard masks and more complex processes, such as bilayer resists. With regard to BEOL processing where damascene patterning is done by etching holes and vias in low-k dielectrics, there are challenges that must be faced in managing the impact of using various types of etch stops and hard masks and different process flows (i.e., via-first vs. trench-first) on factors such as damage, variability and effective k (keff) value. Moreover, etching process flows are more problematic due to increasingly complex material stacks that are needed for BEOL fabrication, wherein in advanced devices, there can be 8 or more layers of materials which must be etched for BEOL fabrication, including, for example, photoresist layers, hard mask layers, antireflective coatings (ARCs), capping layers and etch-stop layers, and porous low-k dielectric.